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ad7470/72 a rev. prd 09/98 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 analog devices, inc., 1998 1.75msps, 4mw 10-bit/12-bit sar adc preliminary technical data preliminary technical data functional block diagram features specified for v dd of 2.7 v to 5.25 v 1.75msps for ad7470 (10-bit) 1.5msps for AD7472 (12-bit) low power: 3mw typ at 1.75msps with 3v supplies 9mw typ at 1.75msps with 5v supplies wide input bandwidth: 70db snr at 500khz input frequency flexible power/throughput rate management no pipeline delays high speed parallel interface shut down mode: 500 n a typ. 24-pin soic and tssop packages general description the ad7470/AD7472 are 10-bit /12-bit high speed, low power, successive-approximation adcs. the parts operate from a single 2.7 v to 5.25 v power supply and feature throughput rates up to 1.5msps for the 12-bit AD7472 and up to 1.75msps for the 10-bit ad7470. the parts contain a low-noise, wide bandwidth track/hold amplifier which can handle input frequencies in excess of 1mhz. the conversion process and data acquisition are controlled using standard control inputs allowing easy interfacing to mi- croprocessors or dsps. the input signal is sampled on the falling edge of convst and conversion is also initiated at this point. the busy goes high at the start of conversion and goes low 465ns later to indicate that the conversion is complete. there are no pipelined delays associated with the part. the conversion result is accessed via standard cs and rd signals over a high speed parallel interface. the ad7470/AD7472 uses advanced design techniques to achieve very low power dissipation at high throughput rates. with 3v supplies and 1.75msps throughput rate, the parts consume just 1ma. with 5v supplies and 1.75msps, the current consumption is 1.8ma. the part also offers flexible power/throughput rate management. operating the part with 3v supplies and 500ksps throughput reduces the current con- sumption to 0.5ma. at 5v supplies and 500ksps, the part consumes 0.8ma. it is also possible to operate the parts in an auto shutdown mode, where the part powers up to do a conversion and auto- matically enters shutdown mode at the end of conversion. using this method allows very low power dissipation numbers at lower throughput rates. in this mode, the parts can be oper- ated with 3v supplies at 100ksps, and consume an average current of just 150ua. at 5v supplies and 100ksps, the average current consumption is 270ua. the analog input range for the part is 0 to ref in. the +2.5v reference is applied externally to the ref in pin. the conver- sion rate is determined by the externally-applied clock. product highlights 1.high throughput with low power consumption the ad7470 offers 1.75msps throughput and the AD7472 offers 1.5msps throughput rates with 3mw power consumption. 2. flexible power/throughput rate management the conversion rate is determined by an externally-applied clock allowing the power to be reduced as the conversion rate is reduced. the part also features an autoshutdown mode to maximize power efficiency at lower throughput rates. 3. no pipeline delay. the part features a standard successive-approximation adc with accurate control of the sampling instant via a convst input and once off conversion control. ad7470 is a 10 bit part with db0 to db9 as outputs AD7472 is a 12 bit part with db0 to db11 as outputs t/h vin ad7470/AD7472 avdd 10/12-bit successive approximation adc ref in db0 db9 (db11) clk in control logic c o n v s t output drivers vdrive busy c s r d agnd dgnd dvdd
C2C rev. prd ad7470Cspecifications 1 ( v dd = +2.7 v to +5.25 v, ref in = 2.5 v, f clk in = 28 mhz unless otherwise noted; t a = t min to t max , unless otherwise noted.) preliminary technical data parameter a version 1 units test conditions/comments dynamic performance signal to noise + distortion (sinad) 2 58 db min f in =500khz sine wave, f s = 1.75msps signal to noise ratio (snr) 2 59 db min f in =500khz sine wave, f s = 1.75msps total harmonic distortion (thd) C70 db max f in =500khz sine wave, f s = 1.75msps peak harmonic or spurious noise (sfdr) C70 db max f in =500khz sine wave, f s = 1.75msps intermodulation distortion (imd) second order terms C75 db typ third order terms C75 db typ aperture delay tbd ns typ aperture jitter tbd ns typ full power bandwidth 20 mhz typ dc accuracy resolution 10 bits integral nonlinearity 1 lsb max differential nonlinearity 0.9 lsb max guaranteed no missed codes to 10 bits. offset error 1 lsb max gain error 1 lsb max analog input input voltage ranges 0 to ref in volts dc leakage current 1 a max input capacitance 20 pf typ reference input ref in input voltage range 2.5 v +/-1% for specified performance dc leakage current 1 a max input capacitance 20 pf typ logic inputs (vdd=5) (vdd=3) volts input high voltage, v inh 2.8 2.4 v min input low voltage, v inl 0.4 0.4 v max input current, i in 1 1 a max typically 10 na, v in = 0 v or v dd input capacitance, c in 3 10 10 pf max logic outputs output high voltage, v oh v drive -0.2 v min i source = 200 a output low voltage, v ol 0.4 v max i sink =200ma floating-state leakage current 10 a max v dd = 2.7 v to 5.25 v floating-state output capacitance 10 pf max output coding straight(natural) binary conversion rate conversion time 12 clk in cycles 428ns with clk in at 28mhz track/hold acquisition time 100 ns max throughput rate 1.75 msps max conversion time + acquisition time. clk in at 28mhz
C3C rev. prd preliminary technical data ( v dd = +2.7 v to +5.25 v, ref in = 2.5 v, f clk in = 28 mhz unless otherwise noted; t a = t min to t max , unless otherwise noted.) ad7470Cspecifications 1 parameter a version units test conditions/comments power requirements v dd +2.7/+5.25 v min/max i dd 4 digital i/ps = 0v or dv dd normal mode 2.2 ma max typically 1.8ma. v dd = 4.75v to 5.25v. f s =1.75msps normal mode 1.33 ma max typically 1ma. v dd = 2.7v to 3.3v. f s =1.75msps shutdown mode 1 a max clk in =0v or dv dd power dissipation 4 digital i/ps = 0v or dv dd normal mode 11 mw max v dd = 5v. 4 mw max v dd = 3v shutdown mode 5 uw max v dd = 5 v. clk in =0v or dv dd 3 w max v dd = 3 v. clk in =0v or dv dd notes 1 temperature ranges as follows: a, b versions: C40c to +85c. 2 snr calculation includes distortion and noise components. 3 sample tested @ +25c to ensure compliance. 4 see power versus throughput rate section. specifications subject to change without notice.
C4C rev. prd AD7472Cspecifications 1 ( v dd = +2.7 v to +5.25 v, ref in = 2.5 v, f clk in = 28 mhz unless otherwise noted; t a = t min to t max , unless otherwise noted.) preliminary technical data parameter a version 1 units test conditions/comments dynamic performance signal to noise + distortion (sinad) 2 69 db min f in =500khz sine wave, f s = 1.5msps signal to noise ratio (snr) 2 70 db min f in =500khz sine wave, f s = 1.5msps total harmonic distortion (thd) C76 db max f in =500khz sine wave, f s = 1.5msps peak harmonic or spurious noise (sfdr) C76 db max f in =500khz sine wave, f s = 1.5msps intermodulation distortion (imd) second order terms C78 db typ third order terms C78 db typ aperture delay tbd ns typ aperture jitter tbd ns typ full power bandwidth 20 mhz typ dc accuracy resolution 12 bits integral nonlinearity 1 lsb max differential nonlinearity 0.9 lsb max guaranteed no missed codes to 12 bits. offset error 3 lsb max gain error 3 lsb max analog input input voltage ranges 0 to ref in volts dc leakage current 1 a max input capacitance 20 pf typ reference input ref in input voltage range 2.5 v +/-1% for specified performance dc leakage current 1 a max input capacitance 20 pf typ logic inputs (vdd=5) (vdd=3) volts input high voltage, v inh 2.8 2.4 v min input low voltage, v inl 0.4 0.4 v max input current, i in 1 1 a max typically 10 na, v in = 0 v or v dd input capacitance, c in 3 10 10 pf max logic outputs output high voltage, v oh v drive -0.2 v min i source = 200 a output low voltage, v ol 0.4 v max i sink =200ma floating-state leakage current 10 a max v dd = 2.7 v to 5.25 v floating-state output capacitance 10 pf max output coding straight(natural) binary conversion rate conversion time 14 clk in cycles 500ns with clk in at 28mhz track/hold acquisition time 100 ns max throughput rate 1.5 msps max conversion time + acquisition time. clk in at 28mhz
C5C rev. prd preliminary technical data ( v dd = +2.7 v to +5.25 v, ref in = 2.5 v, f clk in = 28 mhz unless otherwise noted; t a = t min to t max , unless otherwise noted.) AD7472Cspecifications 1 parameter a version units test conditions/comments power requirements v dd +2.7/+5.25 v min/max i dd 4 digital i/ps = 0v or dv dd normal mode 2.2 ma max typically 1.8ma. v dd = 4.75v to 5.25v. f s =1.5msps normal mode 1.33 ma max typically 1ma. v dd = 2.7v to 3.3v. f s =1.5msps shutdown mode 1 ua max clk in =0v or dv dd power dissipation 4 digital i/ps = 0v or dv dd normal mode 11 mw max v dd = 5v. 4 mw max v dd = 3v shutdown mode 5 uw max v dd = 5 v. clk in =0v or dv dd 3 uw max v dd = 3 v. clk in =0v or dv dd notes 1 temperature ranges as follows: a, b versions: C40c to +85c. 2 snr calculation includes distortion and noise components. 3 sample tested @ +25c to ensure compliance. 4 see power versus throughput rate section. specifications subject to change without notice.
ad7470/72 C6C rev. prd preliminary technical data preliminary technical data limit at t min , t max parameter ad7470 AD7472 units description f clk 2 1 1 khz min 28 28 mhz max t convert 12* t clk 14* t clk t clk = 1/f clk in 428 500 ns max f clk in = 28mhz t wakeup 1 1 us max wakeup time t acq 100 100 ns max acquisition time t 1 15 15 ns min convst pulse width t 2 10 10 ns min convst to busy delay t 3 0 0 ns max busy to cs setup time t 4 3 0 0 ns max cs to rd setup time t 5 30 30 ns min rd pulse width t 6 4 25 25 ns min data access time after falling edge of rd t 7 5 5 5 ns min bus relinquish time after rising edge of rd t 8 0 0 ns max cs to rd hold time timing specifications 1 notes 1 sample tested at +25c to ensure compliance. all input signals are specified with tr = tf = 5 ns (10% to 90% of v dd ) and timed from a voltage level of 1.6 volts. see figure 2. 2 mark/space ratio for the clk input is 40/60 to 60/40. 3 measured with the load circuit of figure 1 and defined as the time required for the output to cross 0.8 v or 2.0 v. 4 t 7 is derived form the measured time taken by the data outputs to change 0.5 v when loaded with the circuit of figure 1. the measured number is then extrapo- lated back to remove the effects of charging or discharging the 50 pf capacitor. this means that the time, t 7 , quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. specifications subject to change without notice. ( v dd = +2.7 v to +5.25 v, ref in = 2.5 v; t a = t min to t max , unless otherwise noted.) figure 1. load circuit for digital output timing specifications +1.6v i ol 200a 200a i oh to output pin c l 50pf figure 2. ad7470/AD7472 timing diagram t 1 t 2 t convert t 3 t 4 t 5 t 6 t 7 t 8 convst busy dbx cs rd
ad7470/72 C7C rev. prd preliminary technical data preliminary technical data figure 3. ad7470/AD7472 wake-up timing diagram (burst clock) convst busy cs rd dbx t convert t 3 t 4 t 8 t 5 t 6 t 7 t wakeup t convert t 2 clk in
ad7470/72 C8C rev. prd preliminary technical data preliminary technical data caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the xx0000 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. ordering guide resolution package model range (bits) option 1 branding ad7470aru -40c to +85c 10 ru-24 AD7472ar -40c to +85c 12 r-24 AD7472aru -40c to +85c 12 ru-24 eval-ad7470cb 2 evaluation board eval-AD7472cb 2 evaluation board eval-control board 3 controller board notes 1 r = soic; ru = tssop. 2 this can be used as a stand-alone evaluation board or in conjunction with the eval-control board for evaluation/ demonstration purposes. 3 this board is a complete unit allowing a pc to control and communicate with all analog devices evaluation boards ending in the cb designators. absolute maximum ratings `1 (t a = +25 o c unless otherwise noted) av dd to agnd/dgnd ................................. -0.3v to +7v dv dd to agnd/dgnd ................................. -0.3v to +7v v drive to agnd/dgnd ............................... -0.3v to +7v av dd to dv dd ............................................. -0.3v to +0.3v v drive to dv dd .......................................... -0.3v to +0.3v agnd to dgnd ...................................... -0.3v to +0.3v analog input voltage to agnd ......... -0.3v to avdd+0.3v digital input voltage to dgnd ......... -0.3v to dvdd+0.3v ref in to agnd ............................ -0.3v to avdd+0.3v input current to any pin except supplies 2 ............... 10ma operating temperature range commercial (a version) ........................... -40 o c to +85 o c storage temperature range ................... -65 o c to +150 o c junction temperature ........................................ +150 o c soic, tssop package dissipation ..................... +450mw q ja thermal impedance ... 75 o c/w (soic) 115 o c/w (tssop) q jc thermal impedance ..... 25 o c/w (soic) 35 o c/w (tssop) lead temperature, soldering vapor phase (60 secs) ........................................... +215 o c infared (15 secs) ................................................ +220 o c notes 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 transient currents of up to 100 ma will not cause scr latch up.
ad7470/72 C9C rev. prd preliminary technical data preliminary technical data db9 db10 dgnd dv dd ref in cs db11(msb) av dd agnd db3 14 1 2 24 23 5 6 7 20 19 18 3 4 22 21 817 916 10 15 11 top view (not to scale) 11 12 13 AD7472 db2 db1 clk in busy db0 (lsb) db4 v in rd convst db5 v drive db6 db7 db8 ad7470 pin configuration ad7470 pin configuration ad7470 pin configuration ad7470 pin configuration ad7470 pin configuration AD7472 pin configuration AD7472 pin configuration AD7472 pin configuration AD7472 pin configuration AD7472 pin configuration db7 db8 dgnd dv dd ref in cs db9(msb) av dd agnd db1 14 1 2 24 23 5 6 7 20 19 18 3 4 22 21 817 916 10 15 11 top view (not to scale) 11 12 13 ad7470 db0 (lsb) nc clk in busy nc db2 v in rd convst db3 v drive db4 db5 db6 nc = no connect
ad7470/72 C10C rev. prd preliminary technical data preliminary technical data pin function description pin mnemonic function cs chip select. active low logic input used in conjunction with rd to access the conversion result. the conversion result is placed on the data bus following the falling edge of both cs and rd . cs and rd are both connected to the same and gate on the input so the signals are interchangeable. cs can be hardwired permantly low. rd read input. logic input used in conjunction with cs to access the conversion result.the conversion result is placed on the data bus following the falling edge of both cs and rd . cs and rd are both connected to same and gate on the input so the signals are interchangeable. cs and rd can be hardwired permanently low in which case, the data bus is always active and the result of the new conversion are clocked out subsequent to the busy line going low. convst conversion start input. logic input used to initiate conversion. the input track/hold amplifier goes from track mode to hold mode on the falling edge of convst and the conversion process is initi ated at this point. the conversion input can be as narrow as 15ns. if the convst input is kept low for the duration of conversion and is still low at the end of conversion, the part will automatically enter a shutdown mode. if the part enters this shutdown mode, the next rising edge of convst wakes the part up. wake-up time for the part is typically 1 m s. clk in master clock input. the clock source for the conversion process is applied to this pin. conversion time for the AD7472 takes 14 full clock cycles while conversion time for the ad7470 takes 12 full clock cycles. the frequency of this master clock input therefore determines the conversion time and achievable throughput rate. the frequency range for this clock input is from 1khz to 28mhz. busy busy output. logic output indicating the status of the conversion process. the busy signal goes high from the falling edge of convst and stays high for the duration of conversion. once conver- sion is complete and the conversion result is in the output register, the busy line returns low. the track/hold returns to track mode prior to the falling edge of busy and the acquisition time for the part begins at this point. if the convst input is still low when busy goes low, the part automati- cally enters its shutdown mode on the falling edge of busy. ref in reference input. an external reference must be applied to this input. the voltage range for the exter- nal reference is 2.5v 1% for specified performance. av dd analog supply voltage, +2.7v to +5.25v. this is the only supply voltage for all analog circuitry on the ad7470/72. the av dd and dv dd voltages should ideally be at the same potential and must not be more than 0.3v apart even on a transient basis. this supply should be decoupled to agnd. dv dd digital supply voltage, +2.7v to +5.25v. this is the supply voltage for all digital circuitry on the ad7470/72 apart from the output drivers. the dv dd and av dd voltages should ideally be at the same potential and must not be more than 0.3v apart even on a transient basis. this supply should be decoupled to dgnd. agnd analog ground. ground reference point for all analog circuitry on the ad7470/72. all analog input signals and any external reference signal should be referred to this agnd voltage. the agnd and dgnd voltages should ideally be at the same potential and must not be more than 0.3v apart even on a transient basis. dgnd digital ground. this is the ground reference point for all digital circuitry on the ad7470/AD7472. the dgnd and agnd voltages should ideally be at the same potential and must not be more than 0.3v apart even on a transient basis. v in analog input. single-ended analog input channel. the input range is 0v to refin. the analog input presents a high dc input impedance. v drive supply voltage for the output drivers, +2.7v to +5.25v. this voltage determines the output high voltage for the data output pins. it allows the avdd and dvdd to operate at 5v (and maximize the input signal if required) while the digital outputs can interface to 3v logic. db0-db9/11 data bit 0 to data bit 9 (ad7470) and db11 (AD7472). parallel digital outputs which provide the conversion result for the part. these are three-state outputs which are controlled by cs and rd . the output high voltage level for these outputs is determined by the v drive input.
ad7470/72 C11C rev. prd preliminary technical data preliminary technical data terminology integral nonlinearity this is the maximum deviation from a straight line passing through the endpoints of the adc transfer function. the endpoints of the transfer function are zero scale, a point 1/2 lsb below the first code transition, and full scale, a point 1/2 lsb above the last code transition. differential nonlinearity this is the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. offset error this is the deviation of the first code transition (00 . . . 000) to (00 . . . 001) from the ideal, i.e agnd + 1lsb gain error the last transition should occur at the analog value 1 1/2 lsb below the nominal full scale. the first transition is a 1/2 lsb above the low end of the scale (zero in the case of ad7470/74). the gain error is the deviation of the actual difference between the first and last code transitions from the ideal difference between the first and last code transitions. track/hold acquisition time the track/hold amplifier returns into track mode after the end of conversion. track/hold acquisition time is the time required for the output of the track/hold amplifier to reach its final value, within 1/2 lsb, after the end of conversion. signal to (noise + distortion) ratio this is the measured ratio of signal to (noise + distortion) at the output of the a/d converter. the signal is the rms ampli- tude of the fundamental. noise is the sum of all nonfundamental signals up to half the sampling frequency (f s / 2), excluding dc. the ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. the theoretical signal to (noise + distortion) ratio for an ideal n-bit converter with a sine wave input is given by: signal to ( noise + distortion ) = (6.02 n + 1.76) db thus for a 12-bit converter, this is 74 db and for a 10-bit converter is 62db. total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of harmonics to the fundamental. for the ad7470/72, it is defined as: where v 1 is the rms amplitude of the fundamental and v 2 , v 3 , v 4 , v 5 and v 6 are the rms amplitudes of the second through the sixth harmonics. peak harmonic or spurious noise peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the adc output spectrum (up to f s /2 and excluding dc) to the rms value of the fundamental. normally, the value of this specification is deter- mined by the largest harmonic in the spectrum, but for adcs where the harmonics are buried in the noise floor, it will be a noise peak. intermodulation distortion with inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa nfb where m, n = 0, 1, 2, 3, etc. intermodulation distortion terms are those for which neither m nor n are equal to zero. for example, the second order terms include (fa + fb) and (fa C fb), while the third order terms include (2fa + fb), (2fa C fb), (fa + 2fb) and (fa C 2fb). the ad7470/72 are tested using the ccif standard where two input frequencies near the top end of the input bandwidth are used. in this case, the second order terms are usually distanced in frequency from the original sine waves while the third order terms are usually at a frequency close to the input frequencies. as a result, the second and third order terms are specified separately. the calculation of the intermodulation distortion is as per the thd specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in dbs. psr (power supply rejection) variations in power supply will affect the full-scale transition, but not the conveter's linearity. power supply rejection is the maximum change in the full-scale transition point due to a change in power-supply voltage from the nominal value. thd (db ) = 20 log v 2 2 + v 3 2 + v 4 2 + v 5 2 + v 6 2 v 1
ad7470/72 C12C rev. prd preliminary technical data preliminary technical data outline dimensions dimensions shown in inches and (mm). 24 13 12 1 0.6141 (15.60) 0.5985 (15.20) 0.4193 (10.65) 0.3937 (10.00) 0.2992 (7.60) 0.2914 (7.40) pin 1 seating plane 0.0118 (0.30) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.1043 (2.65) 0.0926 (2.35) 0.0500 (1.27) bsc 0.0125 (0.32) 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) 8 0 0.0291 (0.74) 0.0098 (0.25) x 45 24 13 12 1 0.311 (7.90) 0.303 (7.70) 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) pin 1 seating plane 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) bsc 0.0433 (1.10) max 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) 8 0 24-lead soic (r-24) 24-lead soic (r-24) 24-lead soic (r-24) 24-lead soic (r-24) 24-lead soic (r-24) 24-lead tssop (ru-24) 24-lead tssop (ru-24) 24-lead tssop (ru-24) 24-lead tssop (ru-24) 24-lead tssop (ru-24)
adendum samples whose brand include the date code 9830 and 9838 on line 2, have an identified metastability problem which results in one conversion in approx. 1.2million giving an incorrect result. this problem has been corrected on subsequent parts.

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